peter

10/19上課 最後的測試程式

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clocl2(b);
always
#1 C=a&b;
endmodule
module system_clock(clk);
parametor PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end

always@(posedge clk)
if($time>1000) #(PERIOD-1) $stops

endmodule

posted by 瑋哲(水果奶奶) @ 3:04 下午